题解 | #时钟分频（偶数）#

用DFF写

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//

reg clk_div2 ;
reg clk_div4 ;
reg clk_div8 ;
always @ (posedge clk_in or negedge rst) begin
	if (!rst) 
		clk_div2 <= 1'b0;
	else 
		clk_div2 <= ~ clk_div2;
end

always @ (posedge clk_div2 or negedge rst) begin
	if (!rst) 
		clk_div4 <= 1'b0;
	else 
		clk_div4 <= ~ clk_div4;
end

always @ (posedge clk_div4 or negedge rst) begin
	if (!rst) 
		clk_div8 <= 1'b0;
	else 
		clk_div8 <= ~ clk_div8;
end

assign clk_out2 = clk_div2;
assign clk_out4 = clk_div4;
assign clk_out8 = clk_div8;
//*************code***********//
endmodule

用CNT写

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
	reg [1:0] cnt_4;
	reg clk_div2 = 0;
	reg clk_div4 = 0;
	reg clk_div8 = 0;
	
	always @ (posedge clk_in or negedge rst) begin
		if (!rst)
			cnt_4 <= 0;
		else if (cnt_4 == 2'b11)
			cnt_4 <= 0;
		else 
			cnt_4 <= cnt_4 + 1;
	end
	
	always @ (posedge clk_in or negedge rst) begin
		if (!rst) clk_div2 <= 0;
		else if (cnt_4 == 2'b00 || cnt_4 == 2'b01 || cnt_4 == 2'b10 || cnt_4 == 2'b11) 
			clk_div2 <= ~ clk_div2;
		else
			clk_div2 <= clk_div2;
			
		if (!rst) clk_div4 <= 0;
		else if (cnt_4 == 2'b00 || cnt_4 == 2'b10 ) 
			clk_div4 <= ~ clk_div4;
		else
			clk_div4 <= clk_div4;
		
		if (!rst) clk_div8 <= 0;
		else if (cnt_4 == 2'b00) 
			clk_div8 <= ~ clk_div8;
		else
			clk_div8 <= clk_div8;
	end
	
	assign clk_out2 = clk_div2;
	assign clk_out4 = clk_div4;
	assign clk_out8 = clk_div8;
//*************code***********//
endmodule