分三段写更为直观
`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [1:0] cnt_4;
reg [7:0] d_reg;
always @ (posedge clk or negedge rst) begin
if (!rst)
cnt_4 <= 2'd0;
else if (cnt_4 == 2'd3)
cnt_4 <= 2'd0;
else
cnt_4 <= cnt_4 + 1;
end
always @ (posedge clk or negedge rst) begin
if (!rst) begin
d_reg <= 0;
input_grant <= 1'b0;
end
else if (cnt_4 == 2'd0) begin
d_reg <= d;
input_grant <= 1'b1;
end
else begin
d_reg <= d_reg;
input_grant <= 1'b0;
end
end
always @ (posedge clk or negedge rst) begin
if (!rst)
out <= 0;
else if (cnt_4 == 2'd0)
out <= d;
else if (cnt_4 == 2'd1)
out <= (d_reg<<2) - d_reg;
else if (cnt_4 == 2'd2)
out <= (d_reg<<3) - d_reg;
else if (cnt_4 == 2'd3)
out <= (d_reg<<3);
else
out <= 0;
end
//*************code***********//
endmodule