题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;
reg [2:0] current_state,next_state;

always@(*)
begin
case(current_state)
s0: next_state = din ? s1 :s0;
s1: next_state = din ? s2 :s0;
s2: next_state = din ? s1 :s3;
s3: next_state = din ? s4 :s0;
s4: next_state = din ? s1 :s0;
default : next_state = s0;
endcase
end
    always @ (posedge clk or negedge rst_n)
    begin
        if(!rst_n)
        begin
        current_state<=s0;
        end
        else
        begin
        current_state<=next_state;
        end
    end
        always@(posedge clk or negedge rst_n)
        begin
            if(!rst_n)
            begin
            Y<=1'b0;
            end
            else
            begin
            Y<= current_state==s4;
            end
        end
endmodule