题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input a,
    output reg match
    );

    reg [7:0] a_temp;
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            a_temp <= 8'd0;
        else
            a_temp <= {a_temp[6:0],a};
    end
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            match <= 1'd0;
        else if(a_temp == 8'b01110001)
            match <= 1'b1;
        else
            match <= 1'b0;
    end
endmodule