`timescale 1ns/1ns module multi_sel( input [7:0]d , input clk, input rst, output reg input_grant, output reg [10:0]out ); //**code// reg [2:0] i; reg [10:0] temp; always @(posedge clk or negedge rst) begin if(!rst) begin input_grant <= 1'b0; out <= 11'd0; i <= 3'd0; temp <= 11'd0; end else begin case(i) 3'd0: begin out <= d; temp <= d; input_grant <= 1'b1; i <= i+1; end 3'd1: begin out <= temp * 3; input_grant <= 1'b0; i <= i+1; end 3'd2: begin out <= temp * 7; i <= i+1; end 3'd3: begin out <= temp * 8; i <= 3'd0; end endcase end end

//**code// endmodule

仿顺序结构，使用了一个简单的状态机