`timescale 1ns/1ns
module odd_div (
input wire rst ,
input wire clk_in,
output wire clk_out5
);
parameter N = 5;
reg [2:0] cnt;
reg clk_n;
always @(posedge clk_in or negedge rst)
begin
if(!rst)
cnt <= 3'b000;
else if (cnt == N-1)
cnt <= 3'b000;
else
cnt <= cnt + 1'b1;
end
always @(posedge clk_in or negedge rst)
begin
if(!rst)
clk_n <= 1'b0;
else if (cnt == (N-1)/2)
clk_n <= ~clk_n;
else if (cnt <= 3'b000)
clk_n <= ~clk_n;
else
clk_n <= clk_n;
end
assign clk_out5 = clk_n;
endmodule