题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns
module width_24to128(
    input                 clk         ,   
    input                 rst_n        ,
    input                valid_in    ,
    input    [23:0]        data_in        ,

     output    reg            valid_out    ,
    output  reg [127:0]    data_out
);
    reg [3:0] cnt;
    reg [119:0] data_reg;

    always @ (posedge clk or negedge rst_n) begin
        if (! rst_n) begin
            cnt <= 4'd0;
        end
        else if (cnt == 4'd15 && valid_in == 1'b1) begin
           cnt <= 4'd1; 
        end
        else if (valid_in == 1'b1) begin
           cnt <= cnt + 1; 
        end
    end
    always @ (posedge clk or negedge rst_n) begin
        if (! rst_n) begin
            data_reg <= 120'd0;
        end
        else if (valid_in == 1'b1) begin
            data_reg <= {data_reg[95:0],data_in} ;
        end
    end

    always @ (posedge clk or negedge rst_n) begin
        if (! rst_n) begin
            valid_out <= 1'b0;
            data_out <= 128'b0;
        end
        else if (cnt == 4'd5 && valid_in == 1'b1) begin
           valid_out <= 1'b1;
            data_out <= {data_reg, data_in[23:16]};
        end
        else if (cnt == 4'd10 && valid_in == 1'b1) begin
           valid_out <= 1'b1;
            data_out <= {data_reg[111:0], data_in[23:8]};
        end
        else if (cnt == 4'd15 && valid_in == 1'b1) begin
           valid_out <= 1'b1;
            data_out <= {data_reg[103:0], data_in[23:0]};
        end
        else begin
           valid_out <= 1'b0; 
        end
    end

endmodule