题解 | #自动贩售机2#

next state logic中注意要引入latch，不然因为d就半个周期，状态转移不了

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
	parameter S00 = 0, S05 = 1, S10 = 2, S15 = 3, S20 = 4, S15_5 = 5, S25_5 = 6;
	reg [2:0] state, last_state_1, next_state;
	reg [1:0] d_neg;
	reg [1:0] d_reg;
	wire [1:0] d;
	
	assign d = {d2,d1};
	
	
	// state traansition
	always @ (posedge clk or negedge rst) begin
		if (!rst) begin
			state <= 3'b0;
			last_state_1 <= 3'b0;
		end
		else begin 
			state <= next_state;
			last_state_1 <= state;
		end
	end
	
	// next state transition logic
	always @ (*) begin
		case (state)
			S00: 
				if (d == 2'b01) next_state = S05;
				else if (d == 2'b10) next_state = S10;
				else next_state = next_state;
			S05:
				if (d == 2'b01) next_state = S10;
				else if (d == 2'b10) next_state = sel ? S15 : S00; 
				else next_state = next_state;
			S10:
				if (d == 2'b01) next_state = sel ? S15 : S00; 
				else if (d == 2'b10) next_state = sel ? S20 : S15_5; 
				else next_state = next_state;
			S15:
				if (d == 2'b01) next_state = sel ? S20 : S00; 
				else if (d == 2'b10) next_state = sel ? S00 : S00; 
				else next_state = next_state;
			S20:
				if (d == 2'b01) next_state = sel ? S00 : S00; 
				else if (d == 2'b10) next_state = sel ? S25_5 : S00; 
				else next_state = next_state;
			S15_5: next_state = S00;
			S25_5: next_state = S00;
			default: next_state = S00;
		endcase
	end
	
	// output logic

	
	always @ (*) begin
		out1 = (state == S00) && (last_state_1 == S10 || last_state_1 == S05 )|| (state == S15_5);
		out2 = (state == S00) && (last_state_1 == S15 || last_state_1 == S20 )|| (state == S25_5);
		out3 = (state == S15_5) || (state == S25_5);
	end
//*************code***********//
endmodule