alt

题目意义不大,手撸门级电路太原始。。。

`timescale 1ns/1ns

module comparator_4(
	input		[3:0]       A   	,
	input	   [3:0]		B   	,
 
 	output	 wire		Y2    , //A>B
	output   wire        Y1    , //A=B
    output   wire        Y0      //A<B
);
    assign Y2 = A>B?1:0;
    assign Y1 = A==B?1:0;
    assign Y0 = A<B?1:0;

endmodule