VL5 信号发生器

描述

题目描述：

请编写一个信号发生器模块，根据波形选择信号wave_choise发出相应的波形：wave_choice=0时，发出方波信号；wave_choice=1时，发出锯齿波信号；wave_choice=2时，发出三角波信号。 模块的接口信号图如下：

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);
    
    reg [4:0] cnt1;
    always@(posedge clk or negedge rst_n) begin: count1
        if(~rst_n)
            cnt1 <= 5'b0;
        else if(cnt1 == 5'd20)
            cnt1 <= 5'b0;
        else
            cnt1 <= cnt1 + 1;
    end
    
    reg [4:0] sequance_wave;
    always@(posedge clk or negedge rst_n) begin: gen_squance_wave
        if(~rst_n)
            sequance_wave <= 5'd0;
        else if(cnt1 <= 5'd10)
            sequance_wave <= 5'd0;
        else
            sequance_wave <= 5'd20;
    end
    
    reg [4:0] tri_wave;
    always@(posedge clk or negedge rst_n) begin: gen_sequance_wave
        if(~rst_n)
            tri_wave <= 5'd0;
        else if(tri_wave == 5'd20)
            tri_wave <= 5'd0;
        else
            tri_wave <= tri_wave + 1;
    end
        
    reg [4:0] juchi_wave;
    always@(posedge clk or negedge rst_n) begin: gen_juchi
        if(~rst_n)
            juchi_wave <= 5'd0;
        else if(cnt1 <= 5'd10)
            juchi_wave <= juchi_wave + 1;
        else
            juchi_wave <= juchi_wave - 1;
    end
    
    always@(posedge clk or negedge rst_n) begin:judge_wave
        if(~rst_n)
            wave <= 5'd0;
        else begin
            case(wave_choise)
                2'd0: wave <= sequance_wave;
                2'd1: wave <= tri_wave;
                2'd2: wave <= juchi_wave;
            endcase
        end
    end
    
  
endmodule