题解 | #状态机-非重叠的序列检测#

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5;
//*************code***********//
reg[2:0] current_state,next_state;
always @(*)
begin
case (current_state)
s0 : next_state = data ? s1 : s0;
s1 : next_state = data ? s1 : s2;
s2 : next_state = data ? s3 : s0;
s3 : next_state = data ? s4 : s2;
s4 : next_state = data ? s5 : s2;
s5 : next_state = data ? s1 : s0;
endcase
end

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
current_state<=s0;
end
else
begin
current_state<= next_state;
end
end

always @ (*)
begin
if(!rst)
begin
flag=1'b0;
end
else
begin
flag = current_state== s5 ? 1'b1 :1'b0;
end
end
//*************code***********//
endmodule

`timescale 1ns/1ns
module testbench();
    reg rst;
	reg clk=1;
	reg data;
	wire out;
	 sequence_test2 u1(
	. clk(clk)  ,
	. rst (rst) ,
	. data (data),
	.flag(out)
);
	always #5 clk = ~clk;  // Create clock with period=10 
  initial begin
  rst=0;data=0;
 #10 rst=1;
 #10 data=1;
 #10 data=0;
 #10 data=1;
 #30 data=0;
 #10 data=1;
 #50 data=0;
 #10 data=1;
 #20 data=0;
 #20 

 $finish;
end  
    
endmodule

题中给出的波形图有误，正确的波形图如下：