无符号数的加减

`timescale 1ns/1ns
module data_minus(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,

	output  reg [8:0]c
);
always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
		c <= 9'd0;
	end
	else if(a > b)begin
		c = a - b;
	end
	else
		c = b - a;

endmodule