`timescale 1ns/1ns
module comparator_4(
input [3:0] A ,
input [3:0] B ,
output reg Y2 , //A>B
output reg Y1 , //A=B
output reg Y0 //A<B
);
always @(*) begin
if(A==B) begin
Y0 = 0;
Y1 = 1;
Y2 = 0;
end
else if(A[3]>B[3]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[3]<B[3]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[2]>B[2]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[2]<B[2]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[1]>B[1]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[1]<B[1]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[0]>B[0]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
end
end
end
end
end
end
end
endmodule
module comparator_4(
input [3:0] A ,
input [3:0] B ,
output reg Y2 , //A>B
output reg Y1 , //A=B
output reg Y0 //A<B
);
always @(*) begin
if(A==B) begin
Y0 = 0;
Y1 = 1;
Y2 = 0;
end
else if(A[3]>B[3]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[3]<B[3]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[2]>B[2]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[2]<B[2]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[1]>B[1]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[1]<B[1]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[0]>B[0]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
end
end
end
end
end
end
end
endmodule