状态机解法

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    parameter S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3, S4 = 3'd4;
    reg [2:0] c_state;
    reg [2:0] n_state;
    
    always@(posedge clk or negedge rst) begin: part1
        if(~rst)
            c_state <= S0;
        else
            c_state <= n_state;
    end
    
    always@(*) begin: part2
        case(c_state)
            S0: n_state <= data ? S1 : S0;
            S1: n_state <= data ? S1 : S2;
            S2: n_state <= data ? S3 : S0;
            S3: n_state <= data ? S4 : S2;
            S4: n_state <= data ? S1 : S2;
            default: n_state <= S0;
        endcase
    end
    
    always@(posedge clk or negedge rst) begin: part3
        if(~rst)
            flag <= 0;
        else if(c_state == S4)
            flag <= 1;
        else
            flag <= 0;
    end

//*************code***********//
endmodule

移位寄存器解法

从波形来看，其实是序列全部到来之后的晚两拍才拉高flag信号，因此用移位寄存器存储全部的输入之后再判断，不需要在序列最后一个元素到来的当拍进行拼位判断。采用移位寄存器的实现方式，代码如下：

timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    reg [3:0] data_r;
    always@(posedge clk or negedge rst) begin: reg_data
        if(~rst)
            data_r <= 4'b0;
        else
            data_r <= {data_r[2:0], data};
    end
    
    always@(posedge clk or negedge rst) begin: gen_flag
        if(~rst)
            flag <= 0;
        else if(data_r == 4'b1011)
            flag <= 1;
        else
            flag <= 0;
    end

//*************code***********//
endmodule

```