1、确定题目要求

Ps 本题题解是按照1000的状态转移进行的，不按照此状态进行，编译器可能报错但没有影响。

2、写出v代码

module huawei7(

input wire clk  ,

input wire rst  ,

output reg clk_out

);

parameter[1:0]  S0=2'd0,

S1=2'd1,

S2=2'd2,

S3=2'd3;

reg[1:0]    state,next_state;

always @ (posedge clk or negedge rst)

begin

if(!rst) state<=S0;

else     state<= next_state;

end

always @ (state)

begin

//default values

next_state=S0;

case (state)

S0: begin

next_state=S1;

clk_out=0;

end

S1: begin

next_state=S2;

clk_out=1;

end

S2: begin

next_state=S0;

clk_out=0;

end

S3: begin

next_state=S0;

clk_out=0;

end

endcase

end

endmodule

````timescale 1ns/1ns

module huawei7(
input wire clk  ,
input wire rst  ,
output reg clk_out
);

parameter[1:0]  S0=2'd0,
S1=2'd1,
S2=2'd2,
S3=2'd3;

reg[1:0]    state,next_state;

always @ (posedge clk or negedge rst)
begin
if(!rst) state<=S0;
else     state<= next_state;
end

always @ (state)
begin
//default values
next_state=S0;
case (state)
S0: begin
next_state=S1;
clk_out=0;
end

S1: begin
next_state=S2;
clk_out=1;
end

S2: begin
next_state=S3;
clk_out=0;
end
S3: begin
next_state=S0;
clk_out=0;
end

endcase
end

endmodule

```