题解 | #状态机与时钟分频#

题解思路

1、确定题目要求

首先考虑输入输出，作为分频电路，有一个时钟输入端，clk,输出端div3,再加一个复位端（这里不加也可）所以输入 clk,rst输出 clk_out再考虑状态转换的问题。4分频占空比0.25，可以为0100或1000都行。

在时钟的作用下，应该不停的在这四种状态下转换，并且输出仅仅依赖于当前的状态,所有的整数分频器都可以按照次方法来实现。

Ps 本题题解是按照1000的状态转移进行的，不按照此状态进行，编译器可能报错但没有影响。

2、写出v代码

module huawei7(

       input wire clk  ,

       input wire rst  ,

       output reg clk_out

);

parameter[1:0]  S0=2'd0,

                S1=2'd1,

                            S2=2'd2,

                S3=2'd3;

reg[1:0]    state,next_state;

always @ (posedge clk or negedge rst)

begin

        if(!rst) state<=S0;

        else     state<= next_state;

end

always @ (state)

begin

        //default values

        next_state=S0;

        case (state)

                S0: begin

                         next_state=S1;

                         clk_out=0;

                    end

                   

                S1: begin

                         next_state=S2;

                         clk_out=1;

                    end

                            

                S2: begin

                         next_state=S0;

                         clk_out=0;

                    end

                            S3: begin

                                     next_state=S0;    

                                     clk_out=0;   

                                end

                    

        endcase

end

endmodule

仿真结果如下：

`timescale 1ns/1ns


module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

parameter[1:0]  S0=2'd0,
                S1=2'd1,
				S2=2'd2,
                S3=2'd3;

reg[1:0]    state,next_state;

always @ (posedge clk or negedge rst)
begin
        if(!rst) state<=S0;
        else     state<= next_state;
end

always @ (state)
begin
        //default values
        next_state=S0;
        case (state)
                S0: begin
                         next_state=S1;
                         clk_out=0;
                    end
                    
                S1: begin
                         next_state=S2;
                         clk_out=1;
                    end
                             
                S2: begin
                         next_state=S3;
                         clk_out=0;
                    end
				S3: begin	
				         next_state=S0;	
				         clk_out=0;	
				    end	
                    
        endcase
end



endmodule

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