题解 | #根据状态转移图实现时序电路#

三段式FSM写法

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

	reg [1:0] state, next_state;
	
	
	// state transition
	always @ (posedge clk or negedge rst_n) begin
        if (!rst_n) begin
			state <= 2'b00;
		end
		else begin
			state <= next_state;
		end
	end
	
	// next_state logic
	
	always @ (*) begin
		next_state = 2'b00;
		case (state)
			2'b00: next_state = C ? 2'b01 : 2'b00;
			2'b01: next_state = C ? 2'b01 : 2'b11;
			2'b10: next_state = C ? 2'b10 : 2'b00;
			2'b11: next_state = C ? 2'b10 : 2'b11;
			default: next_state = state;
		endcase
	end
	
	// output logic
    assign Y = (next_state == 2'b10) | (state == 2'b11);
endmodule