题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    parameter S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3;
    reg [2:0] c_state;
    reg [2:0] n_state;
    always@(posedge clk or negedge rst) begin: part1
        if(~rst)
            c_state <= S0;
        else
            c_state <= n_state;
    end
    
    always@(*) begin: part2
        case(c_state)
            S0: n_state = (data == 1) ? S1:S0;
            S1: n_state = (data == 1) ? S2:S1;
            S2: n_state = (data == 1) ? S3:S2;
            S3: n_state = (data == 1) ? S0:S3;
            default: n_state = S0;
        endcase
    end
    
    always@(posedge clk or negedge rst) begin: part3
        if(~rst)
            flag <= 0;
        else if(c_state == S3 && n_state == S0)
            flag <= 1;
        else
            flag <= 0;
    end

//*************code***********//
endmodule