题解 | #任意小数分频#

简化版答案如下，仿真正确。

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output reg clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
    reg [6:0] cnt_r;
    reg [3:0] cnt_sub_r;


//*************code***********//
    always @(posedge clk_in or negedge rst) begin
        if (!rst) begin
            cnt_r <= 'd0;
            cnt_sub_r <= 'd0;
            clk_out <= 'd0;
        end
        else begin
            cnt_r <= cnt_r == M_N - 'd1 ? 'd0 : cnt_r + 'd1;
            if (cnt_r < c89) begin
                cnt_sub_r <= cnt_sub_r == div_e - 1'd1 ? 'd0: cnt_sub_r + 'd1;
                clk_out <= cnt_sub_r < (div_e >> 1) ? 'd1 : 'd0;
            end
            else begin
                cnt_sub_r <= cnt_sub_r == div_o - 1'd1 ? 'd0: cnt_sub_r + 'd1;
                clk_out <= cnt_sub_r < (div_o >> 1) ? 'd1 : 'd0;
            end
        end
    end
endmodule