题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
    reg [1:0] cnt;
    reg [7:0] data_in_r1;
    always@(posedge clk or negedge rst_n) begin: count_data_in
        if(~rst_n) begin
            cnt <= 2'b0;
            data_in_r1 <= 8'b0;
        end
        else if(valid_in) begin
            cnt <= (cnt == 2) ? 0:cnt + 1;
            data_in_r1 <= data_in;
        end
    end
    
    always@(posedge clk or negedge rst_n) begin: gen_output
        if(~rst_n) begin
            data_out <= 12'b0;
            valid_out <= 0;
        end
        else if(valid_in) begin
            if(cnt == 2'd1) begin
                data_out <= {data_in_r1, data_in[7:4]};
                valid_out <= 1;
            end
            else if(cnt == 2'd2) begin
                data_out <= {data_in_r1[3:0], data_in};
                valid_out <= 1;
            end
            else
                valid_out <= 0;
        end
        else
            valid_out <= 0;
    end
    
endmodule