`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
    reg [3:0] count;
    //计数控制
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            count<='d0;
        else if(valid_in)
            count<=(count==15)?'d0:(count+1);
        else
            count<=count;//
    end
    //valid_out 
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            valid_out<=0;
        end
        else if(valid_in) begin                        //只有数据有效位下进行计数
            if(count=='d5)
                valid_out<=1;
            else if(count=='d10)
                valid_out<=1;
            else if(count=='d15)
                valid_out<=1;
            else
                valid_out<=0;
        end
        else begin
            valid_out<=0;
        end
    end
    //data_out
    reg [119:0] buffer;                                    //三次用到的buffer 分别是120 112 104
    //reg [127:0] buffer;                                    //位宽为128时,其实高八位整个过程都不会被用到
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            buffer<='d0;
            data_out<='d0;
        end
        else if(valid_in) begin                           //所有的数据存储要在数据有效位的情况下
            if(count=='d5) begin
                data_out<={buffer[119:0],data_in[23:16]};
                buffer<={buffer[119:16],data_in[15:0]};   //这里的buffer[119:16] 只是腾位置,其中的数据会被后续的data_in覆盖   拼接不是移位
                //buffer<={buffer[127:16],data_in[15:0]};           
            end
            else if(count=='d10) begin
                data_out<={buffer[111:0],data_in[23:8]};
                buffer<={buffer[119:8],data_in[7:0]};     //buffer[119:8] 会被覆盖   //这里是拼接不是循环移位
                //buffer<={buffer[127:8],data_in[7:0]};
            end
            else if(count=='d15) begin
                data_out<={buffer[103:0],data_in};
                buffer<={buffer[119:24],data_in};         //buffer[119:24]会被覆盖  这里是拼接不是循环移位
                //buffer<={buffer[127:24],data_in};
            end
            else begin
                buffer<={buffer[95:0],data_in};           //这里是循环移位
                //buffer<={buffer[103:0],data_in};
            end
        end
    end
endmodule