题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns
module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);
//	MOORE状态机，输出不只和当前输入有关，还和原态有关。//	记忆

//	实现从左只有序列：1101，不重叠
//	当检测到：1101，Y 输出一个时钟的高脉冲

//	状态机实现
reg		[3:0]	state, n_state;

parameter		s0	= 4'b1111,	//	初态
				s1 	= 4'b0001,
				s2	= 4'b0010,
				s3	= 4'b0100,
				s4	= 4'b1000;

always@(posedge clk or negedge rst_n)	begin
	if(!rst_n)
		state	<= s0;
	else 
		state	<= n_state;
end
//
//always@(state)		begin	//	没有加入 din信号，不可操作.
//	n_state	= 
always@(state or din)	begin
	case(state)
		s0:		if(din == 1)
					n_state		= s1;
				else
					n_state		= s0;
					
		s1:		if(din == 1)
					n_state		= s2;
				else
					n_state		= s0;
					
		s2:		if(din == 0)
					n_state		= s3;
				else
					n_state		= s1;
					
		s3:		if(din == 1)
					n_state		= s4;
				else
					n_state		= s0;
		default:
				n_state		= s0;	
	endcase
end

always@(posedge clk or negedge rst_n)		begin
	if(!rst_n)
		Y	<= 1'b0;
	else if(state == s4)            //  n_state == s4不行，必须要延迟一个clk
		Y	<= 1'b1;
	else
		Y	<= 1'b0;
end

endmodule