题解 | #非整数倍数据位宽转换24to128#

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
reg [3:0] cnt;
reg [127:0] data_reg;
always @ ( posedge clk  or negedge rst_n)
begin
if(!rst_n)
begin
cnt<=4'd0;
end
else if(valid_in)
begin
cnt<=cnt+4'd1;
end
end

always @ (posedge clk  or negedge rst_n)
begin 
if(!rst_n)
begin
data_reg<=128'd0;
end
else 
begin
data_reg<= valid_in==1'b1 ? {data_reg[103:0],data_in} : data_reg;
end 
end

always @(posedge clk  or negedge rst_n )
begin
if(!rst_n)
begin
valid_out<=0;
end
else
begin
valid_out<=(valid_in & (cnt==4'd5|cnt==4'd10|cnt==4'd15));
end
end

always @(posedge clk  or negedge rst_n )
begin
if(!rst_n)
begin
data_out<=0;
end
else 
begin
if(cnt==4'd5)begin data_out<=(valid_in) ? {data_reg[119:0], data_in[23:16]}:data_out; end
if(cnt==4'd10)begin data_out<=(valid_in) ? {data_reg[111:0], data_in[23:8]}:data_out; end
if(cnt==4'd15)begin data_out<=(valid_in) ? {data_reg[103:0], data_in}:data_out; end
end
end
endmodule

`timescale 1ns/1ns

module textbench();
reg clk , rst, valid_in;
reg [23:0] data_in;
wire valid_out;
wire[127:0] data_out;
width_24to128 u0(
              .clk(clk),
              .rst_n(rst),
              .valid_in (valid_in),
              .data_in(data_in),
              .valid_out(valid_out),
              .data_out(data_out)  
            );
 always #5 clk=~clk;
 initial 
 begin
 rst=0;clk=1;valid_in=0 ;
 #25 rst=1;
 #5 valid_in=1;data_in=24'ha0a1a2;
 #10 data_in=24'hb2b1b0;
 #10 data_in=24'hc2c1c0;
 #10 data_in=24'hd2d1d0;
 #10 data_in=24'he2e1e0;
 #10 data_in=24'hf2f1f0;
 #10 valid_in=0;
 #30;
 #10 valid_in=1;data_in=24'ha0a1a2;
 #10 data_in=24'hb2b1b0;
 #10 data_in=24'hc2c1c0;
 #10 data_in=24'hd2d1d0;
 #10 data_in=24'he2e1e0;
 #10 data_in=24'hf2f1f0;
 #10 valid_in=0;
 #30;
 #10 valid_in=1;data_in=24'ha0a1a2;
 #10 data_in=24'hb2b1b0;
 #10 data_in=24'hc2c1c0;
 #10 data_in=24'hd2d1d0;
 #10 data_in=24'he2e1e0;
 #10 data_in=24'hf2f1f0;
 #10 valid_in=0;
 #30;
  #10 valid_in=1;data_in=24'ha0a1a2;
 #10 data_in=24'hb2b1b0;
 #10 data_in=24'hc2c1c0;
 #10 data_in=24'hd2d1d0;
 #10 data_in=24'he2e1e0;
 #10 data_in=24'hf2f1f0;
 #10 valid_in=0;
 #30;
  #10 valid_in=1;data_in=24'ha0a1a2;
 #10 data_in=24'hb2b1b0;
 #10 data_in=24'hc2c1c0;
 #10 data_in=24'hd2d1d0;
 #10 data_in=24'he2e1e0;
 #10 data_in=24'hf2f1f0;
 #10 valid_in=0;
 #30;
 $finish;
 end
endmodule

仿真波形如下：