题解 | #自动贩售机1#

module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5,s6=3'd6;
parameter m1=3'b001,m2=3'b010,m3=3'b100;
reg [1:0] remain;
wire  [2:0]temp;
reg [2:0] current_state,next_state;
reg out;
assign temp={d3,d2,d1};
always @(*)
begin
case(current_state)
s0 :begin  out=1'b0; remain=2'd0; 
            case (temp)
            m1 : next_state =s1;
            m2:  next_state =s2;
            m3:  next_state =s4;
            default: next_state=next_state;
            endcase
     end
s1 :begin  out=1'b0; remain=2'd0; 
            case (temp)
            m1 : next_state =s2;
            m2:  next_state =s3;
            m3:  next_state =s5;
            default: next_state=next_state;
            endcase
     end
            
            
            
s2 :begin  out=1'b0; remain=2'd0; 
            case (temp)
            m1 : next_state =s3;
            m2:  next_state =s4;
            m3:  next_state =s6;
            default: next_state=next_state;
            endcase
     end
s3 :begin  out=1'b1; remain=2'd0; 
            case (temp)
            m1 : next_state =s1;
            m2:  next_state =s2;
            m3:  next_state =s4;
           default: next_state=s0;
            endcase
     end 
s4 :begin  out=1'b1; remain=2'd1; 
            case (temp)
            m1 : next_state =s1;
            m2:  next_state =s2;
            m3:  next_state =s4;
            default: next_state=s0;
            endcase
     end    
s5 :begin  out=1'b1; remain=2'd2; 
            case (temp)
            m1 : next_state =s1;
            m2:  next_state =s2;
            m3:  next_state =s4;
            default: next_state=s0;
            endcase
     end       
s6 :begin  out=1'b1; remain=2'd3; 
            case (temp)
            m1 : next_state =s1;
            m2:  next_state =s2;
            m3:  next_state =s4;
            default: next_state=s0;
            endcase 
            end                
default: next_state=s0;
endcase
end
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
current_state<=s0;
end
else
begin
current_state<=next_state;
end
end
always @(*)
begin
if(!rst)
begin
out1=1'b0;
out2=2'd0;
end
else
begin
out2=remain;
out1=out;
end
end
//*************code***********//
endmodule

`timescale 1ns/1ns
module textbench();
reg clk ,rst,d1,d2,d3;
wire out1;
wire [1:0] out2;
seller1 u0(
	.clk(clk)  ,
	.rst(rst),
	.d1(d1),
	.d2(d2) ,
	.d3(d3),
	
	.out1(out1),
	.out2(out2)
);

always #5 clk=~clk;
   initial
begin
clk=1;rst=0;d1=0;d2=0;d3=0;
#5 rst=1;
#5 d1=1;
#5 d1=0;
#15 d2=1;
#5 d2=0;
#15 d1=1;
#5 d1=0;
#15 d1=1;
#5 d1=0;
#5 d3=1;
#5 d3=0;
#25 d3=1;
#5 d3=0;
#25
$finish;
end

endmodule

仿真图像如下：