题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
reg pre,now;

	always @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
		begin
        now<=1'b0;
		pre<=1'b0;
		down<=1'b0;
		rise<=1'b0;
		end
			else
			begin
			now<=a;
			pre<=now;
			end
	end
always @(*)
begin
			case ({now,pre})
			2'b10:begin rise=1'b1;down=1'b0;end
			2'b01:begin rise=1'b0;down=1'b1;end
			default:begin rise=1'b0; down=1'b0;end
			endcase
end	
endmodule