题解 | #输入序列连续的序列检测#

采用移位寄存器存储输入a的数据，再进行判断即可。

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

    reg [7:0] seq_a;
    always@(posedge clk or negedge rst_n) begin: reg_a
        if(~rst_n) begin
            seq_a <= 8'b0;
        end
        else begin
            seq_a <= {seq_a[6:0], a};
        end
    end
    
    always@(posedge clk or negedge rst_n) begin: judge_match
        if(~rst_n) 
            match <= 0;
        else if(seq_a == 7'b01110001)
            match <= 1;
        else
            match <= 0;
    end
   
endmodule