题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
    parameter S0 = 2'd0;
    parameter S1 = 2'd1;
    parameter S2 = 2'd2;
    reg [143:0] data_reg;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            data_reg <= 'd0;
        end
        else begin
            data_reg <= valid_in?{data_reg[119:0],data_in}:data_reg;
        end
    end
    reg [3:0] cnt;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            cnt <= 'd0;
        end
        else begin
            cnt <= valid_in?(cnt+'d1):cnt;
        end
    end
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            data_out <= 'd0;
            valid_out <= 1'b0;
        end
        else begin
            case(cnt)
                'd5: begin
                    data_out <= &valid_in?{data_reg[119:0],data_in[23:16]}:data_out;
                    valid_out <= &valid_in?1'b1:1'b0;
                end
                'd10: begin
                    data_out <= valid_in?{data_reg[111:0],data_in[23:8]}:data_out;
                    valid_out <= valid_in?1'b1:1'b0;
                end
                'd15: begin
                    data_out <= valid_in?{data_reg[103:0],data_in}:data_out;
                    valid_out <= valid_in?1'b1:1'b0;
                end
                default: begin
                    data_out <= data_out;
                    valid_out <= 1'b0;
                end
            endcase
        end
    end
endmodule