题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
//上升沿检测电路
logic data_in_r; 
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
	data_in_r <= 'b0;
end
else if (data_in != data_in_r) begin
	data_in_r <= data_in;
end
end

wire data_re;
assign data_re = data_in & (!data_in_r);

always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
	data_out <= 'b0;
end
else if (data_out != data_re) begin
	data_out <= data_re;
end
end

endmodule