`timescale 1ns/1ns

module counter_16(
   input                clk   ,
   input                rst_n ,
 
   output   reg  [3:0]  Q      
);

//reg [3:0] cnt;

always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    Q <= 'd0;
  end

  else begin
    Q <= Q + 'd1;
  end
end

endmodule