`timescale 1ns/1ns module function_mod( input clk, input rst_n, input [3:0]a, input [3:0]b,

output [3:0]c,
output [3:0]d

); function [3:0] data_in; input [3:0] x; reg [3:0] data_in; begin data_in[0] = x[3]; data_in[1] = x[2]; data_in[2] = x[1]; data_in[3] = x[0]; end endfunction

assign c = rst_n ? data_in(a) : 4'b0;
assign d = rst_n ? data_in(b) : 4'b0;

endmodule