题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg [4:0] out;
reg validout;
reg [15:0] data_clock;
always@(posedge clk or negedge rst) begin
    if(!rst) begin
        out <= 0;
        validout <= 0;
        data_clock <= 0;
    end
    else begin
        case(sel)
            2'd0: begin
                out <= 0;
                validout <= 0;
                data_clock <= d;
            end
            2'd1:begin
                out <= data_clock[3:0] + data_clock[7:4];
                validout <= 1;
            end
            2'd2:begin
                out <= data_clock[3:0] + data_clock[11:8];
                validout <= 1;
            end
            2'd3:begin
                out <= data_clock[3:0] + data_clock[15:12];
                validout <= 1;
            end
            default:begin
                out <= 0;
                validout <= 0;
            end
        endcase
    end
end
//*************code***********//
endmodule