module count_module( //秒表计数器 input clk, input rst_n, output reg [5:0]second, output reg [5:0]minute );
reg flag1 = 0;
always@(posedge clk or negedge rst_n)begin
if(rst_n == 1'b0)begin
second <= 6'd0;
end
else begin
if(second >= 6'd60)begin
second <= 6'd1;
flag1 <= 1'b1;
end
else begin
second <= second + 1'b1;
flag1 <= 1'b0;
end
end
end
always@(posedge flag1 or negedge rst_n)begin
if(rst_n == 1'b0)
minute <= 6'd0;
else begin
if(minute >= 6'd59)begin
minute <= 6'd60;
end
else begin
minute <= minute + 1;
end
end
end
endmodule