题解 | #逻辑运算2#

`timescale 1ns/1ns

module top_module (
	input a,
	input b,
	input c,
	input d,
	output e,
	output f );
wire temp0,temp1,temp2;

assign temp0=a&b,  temp1=c^d,  temp2=temp0^temp1;

assign e=temp0~^temp1;

assign f=d|temp2;

endmodule