`timescale 1ns/1ns
module count_module(
input clk,
input rst_n,
output reg [5:0]second,
output reg [5:0]minute
);
always@(posedge clk or negedge rst_n) begin: count_second
if(~rst_n)
second <= 6'b0;
else if(minute < 6'd60)
second <= (second == 6'd60) ? 6'd1:second+1;
else
second <= 6'b0;
end
always@(posedge clk or negedge rst_n) begin: count_minu
if(~rst_n)
minute <= 6'd0;
else if(minute < 6'd60)
minute <= (second == 6'd60) ? minute+1:minute;
else
minute <= minute;
end
endmodule