module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
reg [1:0] cnt;
reg [7:0] temp;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt<=2'd0;
end
else 
begin
if(valid_in)
begin
cnt<= cnt==2'd2 ? 2'd0: cnt+2'd1;
end
end
end

always@ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
 temp<=8'd0;
end 
else
begin
temp<=data_in;
end
end

always@ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
 valid_out<=1'b0;
end 
else
begin
valid_out<= (valid_in  && cnt!=2'd0);
end
end

always@ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
data_out<=12'd0;
end
else if(valid_in && cnt==2'd1)
begin
data_out<={temp,data_in[7:4]};
end
else if(valid_in && cnt==2'd2)
begin
data_out<={temp[3:0],data_in};
end
end
endmodule
`timescale 1ns/1ns

module textbench();
reg clk , rst, valid_in;
reg [7:0] data_in;
wire valid_out;
wire[11:0] data_out;
width_8to12 u0(
              .clk(clk),
              .rst_n(rst),
              .valid_in (valid_in),
              .data_in(data_in),
              .valid_out(valid_out),
              .data_out(data_out)  
            );
 always #5 clk=~clk;
 initial 
 begin
 rst=0;clk=1;valid_in=0 ;
 #25 rst=1;
 #5 valid_in=1;data_in=8'ha0;
 #10 data_in=8'ha1;
 #10 valid_in=0;
 #30 valid_in=1; data_in=8'hb0;
 #10 valid_in=0;
 #30;
 $finish;
 end
endmodule

仿真波形如下: