`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);
reg [3:0] temp;
reg [2:0] count;
reg out;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
count<=0;
end
else 
begin
count<= count==3'd4 ? 3'd1 : count+3'd1;
end
end 
assign valid_in= count==3'd4;

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
temp=4'd0;
out<=0;
end
else
begin
temp<=  count==3  ? d : temp;
end
end
always @(*)
begin
case (count)
1 : out=temp[2];
2 : out=temp[1];
3 : out=temp[0];
4 : out=temp[3];
default : out=0;
endcase 
end
assign dout=out;
endmodule


`timescale 1ns/1ns
module textbench();
reg clk,rst;
reg[3:0] d;
wire  valid_in,dout;
huawei5 u0 (
	clk  ,
	rst  ,
	d ,
	valid_in ,
    dout
	);

always #5clk=~clk;

 initial begin
rst=0; clk=0;d=0;
#10 rst=1;
#20 d=4'b1010;
#20 d=4'b0110;
#20 d=4'b1110;
#150
$finish;
end

endmodule

仿真结果如下：