题解 | #使用握手信号实现跨时钟域数据传输#

module data_driver(
	input clk_a,
	input rst_n,
	input data_ack,
	output reg [3:0]data,
	output reg data_req
	);
reg [3:0] counter;	
reg ack0,ack1;
always @(posedge clk_a or negedge rst_n)
begin
if(!rst_n)
begin
ack0<=0;
ack1<=0;
end
else
begin
ack0<=data_ack;
ack1<=ack0;
end
end
always@(posedge clk_a or negedge rst_n)
begin
if(!rst_n)
begin
counter<=0;
end
else if(ack0 &~ack1)
begin
counter<=0;
end
else 
begin
counter<=counter==4 ? counter : counter+1;
end
end
always @(posedge clk_a or negedge rst_n)
begin
if(!rst_n)
begin
data_req<=0;
data<=0;
end
else if (ack0 &~ack1)
begin
data<=data+1;
data_req<=0;
end
else
begin
data<=data;
data_req<=counter==4;
end
end
endmodule
module data_receiver(
	input clk_b,
	input rst_n,
	input data_req,
	input [3:0]data,
	output reg data_ack
	);
reg ack0,ack1;
reg [3:0]temp_data;
always @(posedge clk_b or negedge rst_n)
begin
if(!rst_n)
begin
ack0<=0;
ack1<=0;
end
else
begin
ack0<=data_req;
ack1<=ack0;
end
end
always @(posedge clk_b or negedge rst_n)
begin
if(!rst_n)
begin
out<=0;
data_ack<=0;
end
else if (ack0 &~ack1)
begin
temp_data<=data;
data_ack<=1;
end
else
begin
data_ack<=0;
temp_data<=temp_data;
end
end
endmodule

`timescale 1ns/1ns
module texbench ();
reg clk_a,rst_n,clk_b;
wire ack,req;
wire [3:0]data;
data_driver u0(
	 .clk_a(clk_a),
	 .rst_n(rst_n),
	 .data_ack(ack),
	 .data(data),
	 .data_req(req)
	);
data_receiver u1(
	.clk_b(clk_b),
	.rst_n(rst_n),
	 .data_ack(ack),
	 .data(data),
	 .data_req(req)
	);


always #5 clk_b=~clk_b;
always #10 clk_a=~clk_a;
initial
begin
clk_a=0;rst_n=0;clk_b=0;
#10 rst_n=1;

#800
$finish;
end
endmodule 

仿真结果如下：