用generate 简化代码

module add_4(
   input         [3:0]  A   ,
   input         [3:0]  B   ,
   input                Ci  , 

   output	wire [3:0]  S   ,
   output   wire        Co   
);
    wire [3:0] tmpC;
    genvar i;
    generate
        for (i=0; i<4; i=i+1) begin
            add_full add_full(A[i], B[i], i==0? Ci:tmpC[i-1], S[i], tmpC[i]);
    end
    endgenerate
    
    assign Co = tmpC[3];
    
endmodule