`timescale 1ns/1ns
module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);

always @(*)begin
   casex(I_n)
      9'b111111111 : Y_n = 4'b1111;
      9'b0xxxxxxxx : Y_n = 4'b0110;
      9'b10xxxxxxx : Y_n = 4'b0111;
      9'b110xxxxxx : Y_n = 4'b1000;
      9'b1110xxxxx : Y_n = 4'b1001;
      9'b11110xxxx : Y_n = 4'b1010;
      9'b111110xxx : Y_n = 4'b1011;
      9'b1111110xx : Y_n = 4'b1100;
      9'b11111110x : Y_n = 4'b1101;
      9'b111111110 : Y_n = 4'b1110;
      default      : Y_n = 4'b1111;
   endcase    
end 
     
endmodule

module key_encoder(
      input      [9:0]         S_n   ,         
 
      output wire[3:0]         L     ,
      output wire              GS
);
wire[3:0]temp;
reg [3:0]out;
reg g;
encoder_0 u0(.I_n(S_n[9:1]),.Y_n(temp));
always @(*)begin
   case(temp)
4'b1111: begin g= 1'b0;
if(S_n[0])
begin
g= 1'b0;
out= 0; 
end
else
begin
 g= 1'b1 ;
 out= 0; 
end
end
4'b0110: begin  out= 9; g= 1'B1; end
4'b0111: begin  out= 8; g= 1'B1; end
4'b1000: begin  out= 7; g= 1'B1; end
4'b1001: begin  out= 6; g= 1'B1 ;end
4'b1010: begin  out= 5; g= 1'B1 ;end
4'b1011: begin  out= 4; g= 1'B1 ;end
4'b1100: begin  out= 3; g= 1'B1 ;end
4'b1101: begin  out= 2; g= 1'B1 ;end
4'b1110: begin  out= 1; g= 1'B1 ;end
   endcase    
  
end 
assign GS=g;
assign L=out;


endmodule