题解 | #全加器#

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;

endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

//	half_add
wire		C1;
wire		S1;

//	full_add
wire		C_F;
wire		S_F;

add_half	u1_add_half(
.A			(A		),
.B			(B		),

.S			(S1		),	//	S1 	= A ^ B
.C			(C1		)	//	C1 	= A & B
);

add_half	u2_add_half(
.A			(S1		),
.B			(Ci		),

.S			(S_F	),	//	S_F	= S1 ^ Ci
.C			(C_F	)	//	C_F	= S1 & Ci
);

assign		S 		= S_F;
assign		Co		= C_F + C1;

endmodule