`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);
reg a,b;
always @ (posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        a <=0;
        b <=0;
    end
    else begin
        a <= ~a;
        b <= ~A&(a^b) | ~(a^b)&A;
    end
end
///////这里的赋值根据真值表我还是觉得应该用时序逻辑。但是仿真结果表明组合逻辑是对的。
assign Y = a&b;
 
endmodule