题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [8:0] queue;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		match <= 0;
	end
	else begin
		if ((queue[8:6] == 3'b011) && (queue[2:0] == 3'b110))
			match <= 1;
		else
			match <= 0;
	end
	queue <= {queue[7:0], a};
end

endmodule