`timescale 1ns/1ns //********************************** //主模块 //********************************** module main_mod( input clk, input rst_n, input [7:0]a, input [7:0]b, input [7:0]c,

output [7:0]d

); wire [7:0] data_one; wire [7:0] data_two; compare_two U1( .clk(clk), .rst_n(rst_n), .data_a(a), .data_b(b), .data_c(data_one) ); compare_two U2( .clk(clk), .rst_n(rst_n), .data_a(a), .data_b(c), .data_c(data_two) ); compare_two U3( .clk(clk), .rst_n(rst_n), .data_a(data_one), .data_b(data_two), .data_c(d) );

endmodule

//********************************** //子模块 //********************************** module compare_two( input clk, input rst_n, input [7:0] data_a, input [7:0] data_b,

output reg [7:0] data_c

); always @(posedge clk or negedge rst_n) begin if(!rst_n) data_c <= 8'd0; else if(data_a > data_b) data_c <= data_b; else data_c <= data_a; end // assign data_c = (data_a<data_b) ? data_a:data_b;

endmodule /* //********************************** //测试用例 //********************************** module main_mod_tb(); reg clk; reg rst_n; reg [7:0]a; reg [7:0]b; reg [7:0]c; wire [7:0]d;

always #10 clk = ~clk; initial begin clk = 1'b0; rst_n = 1'b0; #100; rst_n = 1'b1; #10; a=8'd10; b=8'd2; c=8'd25; #1000; $stop; end endmodule */