本题目的知识点很明确,位操作和未拆分,拼接语法没用到哈,还是一个多路选择器,用case就能完成,注意的是输出的信号的类型reg
`timescale 1ns/1ns module data_cal( input clk, input rst, input [15:0]d, input [1:0]sel, output [4:0]out, output validout ); reg out; reg validout; //*************code***********// reg [15:0] r_d; always @ (posedge clk or negedge rst) if (!rst)begin out <= 5'd0; validout <= 1'b0; end else begin case(sel) 2'b00: begin validout <= 1'b0; r_d <= d; out <= 5'd0; end 2'b01: begin validout <= 1'b1; out <=r_d[3:0]+ r_d[7:4]; end 2'b10: begin validout <= 1'b1; out <=r_d[3:0]+ r_d[11:8]; end 2'b11: begin validout <= 1'b1; out <=r_d[3:0]+ r_d[15:2]; end endcase end //*************code***********// endmodule