`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output q
);
//*************code***********//
wire q1;
TFF TFF_inst1(
.data (data),
.clk (clk),
.rst (rst),
.q (q1)
);
TFF TFF_inst2(
.data (q1),
.clk (clk),
.rst (rst),
.q (q)
);
//*************code***********//
endmodule
//T触发器设计
module TFF(
input wire data, clk, rst,
output reg q
);
always @(posedge clk or negedge rst)begin
if(!rst)
q <= 1'b0;
else if(data == 1'b0)
q <= q;
else if(data == 1'b1)
q <= ~q;
end
endmodule



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