题解 | #使用generate…for语句简化代码#

`timescale 1ns/1ns
module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);

//wire [7:0] data;
parameter size = 3'd7;
genvar i;

    generate 
        for(i = 0;i < size + 1; i = i + 1) //i++是格式错误
            begin:bit_reverse
                assign data_out[i] = data_in [size - i];
            end
    endgenerate

    //assign data_out = data;

 
endmodule