题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg[2:0] cnt;
reg[5:0] out;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt=3'd0;
end
else
begin
	if(valid_a)
cnt= (cnt==3'd6) ? 3'd1:cnt+3'd1; 
end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
out=6'd0;
end
else
begin
	if(valid_a)
out={data_a,out[5:1]};
end
end
			always @(*)
			begin
			if(!rst_n)
			begin
			valid_b<=1'd0;
			data_b<=6'd0;
			end
			else
			begin
			valid_b<=(cnt==3'd6);
			data_b<= (cnt==3'd6) ? out : data_b;
			end
			end
					always @(posedge clk or negedge rst_n)
						begin
						if(!rst_n)
						begin
							ready_a<=1'd0;
						end
						else
						begin
						ready_a<=1'd1;
						end
						end
endmodule