module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3;
reg [2:0] state ;

always @ (posedge clk or negedge rst)
begin
if(!rst)
begin
state <=s3;
end
else
begin
case (state)
s0 : state<=s1;
s1 : state<=s2;
s2 : state<=s3;
s3 : state<=s0;
default : state<=s0;
endcase
end
end

always @(*)
begin
if(!rst)
begin
clk_out=0;
end
else
begin
clk_out= state==s0;
end
end
//*************code***********//
endmodule


module texbench ();

reg clk, rst;
wire clk_out;
huawei7 u0(
	clk  ,
	rst  ,
	clk_out
);

always #5 clk=~clk;

initial
begin
clk=0;rst=0;
#12 rst=1;
#500
$finish;
end
endmodule

仿真结果如下：