题解 | #任意奇数倍时钟分频#

module clk_divider
    #(parameter dividor = 5)
(   input clk_in,
    input rst_n,
    output clk_out
);
parameter change_pt=(dividor-1)/2;
parameter width=$clog2(dividor);
reg [width:0] upcnt,downcnt;
reg upclk,downclk;
always @(posedge clk_in or negedge rst_n)
begin
if(!rst_n)
begin
upcnt<=0;
end
else
begin
upcnt<= upcnt==dividor-1 ? 0:upcnt+1;
end
end
    
 always @(negedge clk_in or negedge rst_n)
begin
if(!rst_n)
begin
downcnt<=0;
end
else
begin
downcnt<= downcnt==dividor-1 ? 0:downcnt+1;
end
end

always @(*)
begin
if(!rst_n)
begin
upclk=0;
downclk=0;
end
else
begin
upclk= upcnt<change_pt ? 0 : 1;
downclk=downcnt<change_pt ? 0 : 1;
end
end
assign clk_out=upclk&downclk;
endmodule

`timescale 1ns/1ns
module texbench ();
reg clk,rst;
wire out;
 clk_divider  u0 ( 	
   . clk_in(clk),
   . rst_n(rst),
   .clk_out(out)
);

always # 5 clk=~clk;
initial
begin
#0 clk=0; rst=0;
#12 rst=1;
#300;
$finish;
end
endmodule

仿真结果如下：