`timescale 1ns/1ns module odd_sel( input [31:0] bus, input sel, output check ); //**code//
assign check = (sel ^ (^bus))? 1'b0:1'b1;
//**code// endmodule
^bus 判断bus[31:0]中1的个数是奇数(1)还是偶数(0);
sel == 1 && ^bus == 0 奇校验,bus上1的个数为偶数,check = 1;
sel == 0 && ^bus == 1 偶校验,bus上1的个数为奇数,check = 1;