对于奇数分频电路,主要难点在于50%占空比的实现。单触发沿在奇数分频中是没有办法实现50%占空比的,因此需要考虑使用双边沿加组合逻辑实现50%占空比。
`timescale 1ns/1ns
module odo_div_or
#(parameter N = 7)
(
input wire rst ,
input wire clk_in,
output wire clk_out7
);
//*************code***********//
reg [3:0] cnt;
always@(posedge clk_in or negedge rst) begin: count
if(~rst)
cnt <= 4'b0;
else
cnt <= (cnt == N-1) ? 0 : cnt + 1;
end
reg clkp;
always@(posedge clk_in or negedge rst) begin: clk_posedge
if(~rst)
clkp <= 0;
else if(cnt == (N>>1))
clkp <= 1;
else if(cnt == N-1)
clkp <= 0;
end
reg clkn;
always@(negedge clk_in or negedge rst) begin: clk_negedge
if(~rst)
clkn <= 0;
else if(cnt == (N>>1))
clkn <= 1;
else if(cnt == N-1)
clkn <= 0;
end
assign clk_out7 = clkp | clkn;
//*************code***********//
endmodule